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xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 437
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.36 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register
(USB xHCI—D20:F0)
Address Offset: D4–D7h Attribute: RO, R/WLO
Default Value: 00000000h Size: 32 bits
Note: The R/WL property of this register is controlled by the ACCTRL bit (D20:F0:40h, bit
31).
11.2.37 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register
(USB xHCI—D20:F0)
Address Offset: D8h–dBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Note: Bits 3:0 are located in the Suspend Well.
11.2.38 USB3PRM—USB 3.0 Port Routing Mask Register
(USB xHCI—D20:F0)
Address Offset: DC–DFh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Note: The R/WL property of this register is controlled by the ACCTRL bit (D20:F0:40h, bit
31).
Bit Description
31:15 Reserved.
14:0 USB 2.0 Host Controller Selector Mask (USB2HCSELM) — R/W. This bit field allows the BIOS to
communicate to the OS which USB 2.0 ports can be switched from the EHC controller to the xHC
controller.
When set to 1, the OS may switch the USB 2.0 port between the EHCI and xHCI host controllers by
modifying the corresponding USB2HCSEL bit (D20:F0:D0h, bit 3:0).
When cleared to 0, The OS shall not modify the corresponding USB2HCSEL bit.
Port to bit mapping is in one-hot encoding: that is, bit 0 controls port 1 and so on.
Bit 0 = USB 2.0 Port 0
....
Bit 13 = USB 2.0 Port 13
Bit Description
31:6 Reserved.
5:0 USB 3.0 Port SuperSpeed Enable (USB3PSSEN) — R/W. This field controls whether
SuperSpeed capability is enabled for a given USB 3.0 port.
When set to 1, this bit enables the SuperSpeed terminations and allows the xHC to view the
SuperSpeed connections on the USB port.
Enables PORTSC to see the connects on the ports.
When cleared to 0, the port’s SuperSpeed capability is not visible to the xHC.
Bit 0 = USB 3.0 Port 1
Bit 1 = USB 3.0 Port 2
Bit 2 = N/A
Bit 3 = N/A
Bit 4 = USB 3.0 Port 5
Bit 5 = USB 3.0 Port 6
Bit Description
31:6 Reserved.