Datasheet

xHCI Controller Registers (D20:F0)
436 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.34 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2
(USB xHCI—D20:F0)
Address Offset: CC–CFh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
11.2.35 XUSB2PR —xHC USB 2.0 Port Routing Register
(USB xHCI—D20:F0)
Address Offset: D0–D3h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: Bits 3:0 are located in the Suspend Well.
Bit Description
31:30 Reserved
29:24 OC7 Mapping Each bit position maps OC7 to a set of ports as follows: The OC7 pin is ganged
to the overcurrent signal of each port that has its corresponding bit set. It is software
responsibility to ensure that a given port‘s bit map is set only for one OC pin.
23:22 Reserved
21:16 OC6 Mapping Each bit position maps OC6 to a set of ports as follows: The OC6 pin is ganged
to the overcurrent signal of each port that has its corresponding bit set. It is software
responsibility to ensure that a given port‘s bit map is set only for one OC pin.
15:14 Reserved
13:8 OC5 Mapping Each bit position maps OC5 to a set of ports as follows: The OC5 pin is ganged
to the overcurrent signal of each port that has its corresponding bit set. It is software
responsibility to ensure that a given port‘s bit map is set only for one OC pin.
7:6 Reserved
5:0 OC4 Mapping Each bit position maps OC4 to a set of ports as follows: The OC4 pin is ganged
to the overcurrent signal of each port that has its corresponding bit set. It is software
responsibility to ensure that a given port‘s bit map is set only for one OC pin.
Bit 292827262524
Port 6 5 X X 2 1
Bit 212019181716
Port 6 5 X X 2 1
Bit 13121110 9 8
Port 6 5 X X 2 1
Bit 543210
Port 6 5 X X 2 1
Bit Description
31:15 Reserved.
14:0 USB 2.0 Host Controller Selector (USB2HCSEL) — R/W. Maps a USB 2.0 port to the xHC or EHC
#1 host controller.
When cleared to 0, this bit routes all the corresponding USB 2.0 port pins to the EHCI controller
(D29:F0) and RMH #1. The USB 2.0 port is masked from the xHC and the USB 2.0 port’s OC pin is
routed to the EHCI controller (D29:F0).
When set to 1, this bit routes all the corresponding USB 2.0 pins to the xHC controller. The USB 2.0
port is masked from the EHC and the USB 2.0 port’s OC pin is routed to the xHC controller (D20:F0).
Port to bit mapping is in one-hot encoding; that is, bit 0 controls port 1 and so on.
Bit 0 = USB 2.0 Port 0
....
Bit 13 = USB 2.0 Port 13