Datasheet

xHCI Controller Registers (D20:F0)
432 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.24 PWR_CNTL_STS—Power Management Control / Status
Register (USB xHCI—D20:F0)
Address Offset: 74h–75h Attribute: R/W, R/WC, RO
Default Value: 0000h Size: 16 bits
11.2.25 MSI_CAPID—Message Signaled Interrupt Capability ID
Register (USB xHCI—D20:F0)
Address Offset: 80h Attribute: RO
Default Value: 05h Size: 8 bits
11.2.26 NEXT_PTR2— Next Item Pointer Register #2 (USB xHCI—
D20:F0)
Address Offset: 81h Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
15 PME Status — R/WC. This bit is set when Intel® Xeon® Processor D-1500 Product Family xHC
would normally assert the PME# signal independent of the state of the PME_En bit. Writing a 1 to
this bit will clear it and cause the internal PME to de-assert (if enabled).
Note: This bit must be explicitly cleared by the operating system each time the operating system
is loaded.
This bit is not reset by Function Level Reset.
14:13 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data register.
12:9 Data Select — RO. Hardwired to 0000b indicating it does not support the associated Data register.
8 PME Enable (PME_En)— R/W.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family xHC to generate an internal PME
signal when PME_Status is 1.
Note: This bit must be explicitly cleared by the operating system each time it is initially loaded.
This bit is not reset by Function Level Reset.
7:2 Reserved
1:0 Power State — R/W. This 2-bit field is used both to determine the current power state of EHC
function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3
HOT
state
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs. When in the D3
HOT
state,
Intel® Xeon® Processor D-1500 Product Family must not accept accesses to the EHC memory
range; but the configuration space must still be accessible.
Bit Description
7:0 Capability ID — RO. Hardwired to 05h indicating that this is the start of a MSI Capability structure.
Bit Description
7:0 Next Item Pointer Capability — RO. This register points to the next capability.