Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 431
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.22 NXT_PTR1—Next Item Pointer #1 Register (USB xHCI—
D20:F0)
Address Offset: 71h Attribute: R/W
Default Value: 80h Size: 8 bits
11.2.23 PWR_CAP—Power Management Capabilities Register
(USB xHCI—D20:F0)
Address Offset: 72h–73h Attribute: R/W, RO
Default Value: C9C2h Size: 16 bits
Notes:
1. Normally, this register is read-only to report capabilities to the power management software. To report
different power management capabilities, depending on the system in which Intel® Xeon® Processor D-
1500 Product Family is used, the write access to this register is controlled by the Access Control bit
(D20:F0:40h, bit 31). The value written to this register does not affect the hardware other than changing
the value returned during a read.
2. This register is modified and maintained by BIOS.
3. Reset: core well, but not D3-to-D0 warm reset.
Bit Description
7:0 Next Item Pointer 1 Value — R/W (special). This register defaults to 80h, which indicates that the
next capability registers begin at configuration offset 80h. This register is writable when the ACCTRL
bit (D20:F0:40h, bit 31) is ‘0’. This allows BIOS to effectively hide the next capability registers, if
necessary. This register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Values of 80h implies the next capability is MSI.
Values of 00h implies that the MSI capability is hidden.
Bit Description
15:11 PME Support (PME_SUP) — R/W. This 5-bit field indicates the power states in which the function
may assert PME#. Intel® Xeon® Processor D-1500 Product Family xHC does not support the D1 or
D2 states. For all other states, Intel® Xeon® Processor D-1500 Product Family xHC is capable of
generating PME#. Software should never need to modify this field.
10 D2 Support (D2_SUP) — RO.
0 = D2 State is not supported
9 D1 Support (D1_SUP) — RO.
0 = D1 State is not supported
8:6 Auxiliary Current (AUX_CUR) — R/W. Intel® Xeon® Processor D-1500 Product Family xHC
reports 375 mA maximum suspend well current required when in the D3
COLD
state.
5 Device Specific Initialization (DSI)— RO. Intel® Xeon® Processor D-1500 Product Family
reports 0, indicating that no
device-specific initialization is required.
4Reserved
3 PME Clock (PME_CLK) — RO. Intel® Xeon® Processor D-1500 Product Family reports 0,
indicating that no PCI clock is required to generate PME#.
2:0 Version (VER) — RO. Intel® Xeon® Processor D-1500 Product Family reports 010b, indicating that
it complies with Revision 1.1 of the PCI Power Management Specification.