Datasheet

xHCI Controller Registers (D20:F0)
430 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.20 FL_ADJ—Frame Length Adjustment Register (USB xHCI—
D20:F0)
Address Offset: 61h Attribute: R/W
Default Value: 20h Size: 8 bits
Function Level Reset: No
This feature is used to adjust any offset from the clock source that generates the clock
that drives the SOF counter. When a new value is written into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit (D20:F0:CAPLENGTH + 84h, bit 0) in
the USB_STS register is a 1. Changing value of this register while the host controller is
operating yields undefined results. It should not be reprogrammed by USB system
software unless the default or BIOS programmed values are incorrect, or the system is
restoring the register while returning from a suspended state.
These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.
11.2.21 PWR_CAPID—PCI Power Management Capability ID
Register (USB xHCI—D20:F0)
Address Offset: 70h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
7:6 Reserved — RO. These bits are reserved for future use and should read as 00b.
5:0 Frame Length Timing Value — R/W. Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF
micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
Frame Length (# 480 MHz Clocks)
(decimal)
Frame Length Timing Value (this register)
(decimal)
59488 0
59504 1
59520 2
... ...
59984 31
... ...
60496 63
60480 62
60496 63
Bit Description
7:0 Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.