Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 429
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.17 XHCC—xHC System Bus Configuration Register
(USB xHCI—D20:F0)
Address Offset: 40-43h Attribute: R/W, R/WC
Default Value: 0000F0FDh Size: 32 bits
11.2.18 XHCC2—xHC System Bus Configuration Register 2
(USB xHCI—D20:F0)
Address Offset: 44-47h Attribute: R/WO
Default Value: 00000000h Size: 32 bits
11.2.19 SBRN—Serial Bus Release Number Register (USB xHCI—
D20:F0)
Address Offset: 60h Attribute: RO
Default Value: 30h Size: 8 bits
Bit Description
31:25 Reserved
24 Master/Target Abort SERR (RMTASERR) — R/W. When set, this bit allows the out-of-band error
reporting from the xHCI Controller to be reported as SERR# (if SERR# reporting is enabled) and thus
setting the STS.SSE bit.
23 Unsupported Request Detected (URD) — R/WC. This bit is set by HW when the xHCI Controller
received an unsupported request posted cycle. Once set, this bit is cleared by SW.
22 Unsupported Request Report Enable (URRE) — R/W. When set, this bit allows the URD bit to be
reported as SERR# (if SERR# reporting is enabled) and thus setting the STS.SSE bit.
21:19 Inactivity Initiated L1 Enable (IIL1E) — R/W. If programmed to a non-zero value, the bit field
allows L1 power management to be enabled after the time-out period specified.
000 = Disabled
001 = 32 bb_cclk
010 = 64 bb_cclk
011 = 128 bb_cclk
100 = 256 bb_cclk
101 = 512 bb_cclk
110 = 1024 bb_cclk
111 = 131072 bb_cclk
18 xHC Initiated L1 Enable (XHCIL1E) — R/W.
0 = xHC-initiated L1 power management is disabled
1 = Allows xHC-initiated L1 power management to be enabled
17 D3 Initiated L1 Enable (D3IL1E) — R/W.
0 = PCI device state D3-initiated L1 power management is disabled
1 = Allows PCI device state D3-initiated L1 power management to be enabled
16:0 Reserved
Bit Description
31 OC Configuration Done (OCCFDONE) — R/WO. This bit is used by BIOS to prevent spurious
switching during OC configuration.
Note: This bit must be set by BIOS after configuration of the OC mapping bits is complete. Once
this bit is set, OC mapping shall not be changed by SW.
30:0 Reserved
Bit Description
7:0 Serial Bus Release Number (SBRN)— RO. A value of 30h indicates that this controller follows USB
release 3.0.