Datasheet

xHCI Controller Registers (D20:F0)
428 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.12 SVID—USB xHCI Subsystem Vendor ID Register
(USB xHCI—D20:F0)
Address Offset: 2Ch–2Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
Reset: None
11.2.13 SID—USB xHCI Subsystem ID Register (USB xHCI—
D20:F0)
Address Offset: 2Eh–2Fh Attribute: R/W
Default Value: 0000h Size: 16 bits
Reset: None
11.2.14 CAP_PTR—Capabilities Pointer Register (USB xHCI—
D20:F0)
Address Offset: 34h Attribute: RO
Default Value: 70h Size: 8 bits
11.2.15 INT_LN—Interrupt Line Register (USB xHCI—D20:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
11.2.16 INT_PN—Interrupt Pin Register (USB xHCI—D20:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
Bit Description
15:0 Subsystem Vendor ID (SVID) — R/W. This register, in combination with the xHC Subsystem ID
register, enables the operating system to distinguish each subsystem from the others.
Bit Description
15:0 Subsystem ID (SID) — R/W. BIOS sets the value in this register to identify the Subsystem ID. This
register, in combination with the Subsystem Vendor ID register, enables the operating system to
distinguish each subsystem from other(s).
Bit Description
7:0 Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the xHC
capabilities ranges.
Bit Description
7:0 Interrupt Line (INT_LN) — R/W. This data is not used by Intel® Xeon® Processor D-1500 Product
Family . It is used as a scratchpad register to communicate to software the interrupt line that the
interrupt pin is connected to.
Bit Description
7:0 Interrupt Pin — RO. Bits 3:0 reflect the value of the interrupt pin registers in chipset configuration
space. Bits 7:4 are always 0h