Datasheet

xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 427
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2.8 PMLT—Primary Master Latency Timer Register
(USB xHCI—D20:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
11.2.9 HEADTYP—Header Type Register (USB xHCI—D20:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
11.2.10 MEM_BASE_L—Memory Base Address Low Register
(USB xHCI—D20:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
11.2.11 MEM_BASE_H—Memory Base Address High Register
(USB xHCI—D20:F0)
Address Offset: 14h–17h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
7:0 Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the xHCI controller is
internally implemented with arbitration on an interface (and not PCI), it does not need a master
latency timer.
Bit Description
7 Multi-Function Device — RO. When set to ‘1’ indicates this is a multifunction device:
0 = Single-function device
1 = Multi-function device.
6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout.
Bit Description
31:16 Base Address — R/W. Bits [31:16] correspond to memory address signals [31:16], respectively.
This gives 64 KB of relocatable memory space aligned to 64 KB boundaries.
15:4 Reserved
3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
2:1 Type — RO. Hardwired to 10 indicating that this range can be mapped anywhere within 64-bit
address space.
0 Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address field in this
register maps to memory space.
Bit Description
31:0 Base Address — R/W. Bits [63:32] correspond to memory address signals [63:32], respectively.
This gives 64 KB of relocatable memory space aligned to 64 KB boundaries.