Datasheet
xHCI Controller Registers (D20:F0)
424 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11.2 VID—Vendor Identification Register (USB xHCI—
D20:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
11.2.1 DID—Device Identification Register (USB xHCI—D20:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
11.2.2 PCICMD—PCI Command Register (USB xHCI—D20:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
81h Core NXT_PTR2 Next Item Pointer #2 00h RO
82h–83h Core MSI_MCTL MSI Message Control Register 0086h RO, R/W
84h–87h Core MSI_LMAD MSI Lower Message Address 00000000h RW, RO
88h–8Bh Core MSI_UMAD MSI Upper Message Address 000000h R/W
8Ch–8Fh Core MSI_MD MSI Message Data 00000000h R/W
C0h–C3h Sus U2OCM1 XHCI USB2 Overcurrent Pin Mapping 1 00000000h R/W, RO
C4h–C7h Sus U2OCM2 XHCI USB2 Overcurrent Pin Mapping 2 00000000h R/W, RO
C8h–CBh Sus U3OCM1 XHCI USB3 Overcurrent Pin Mapping 1 00000000h R/W, RO
CCh–CFh Sus U3OCM2 XHCI USB3 Overcurrent Pin Mapping 2 00000000h R/W, RO
D0h–D3h Multiple XUSB2PR xHC USB 2.0 Port Routing 00000000h R/W, RO
D4h–D7h Core XUSB2PRM xHC USB 2.0 Port Routing Mask 00000000h RO, R/WLO
D8h–dBh USB3_PSSEN USB 3.0 Port SuperSpeed Enable
Register
00000000h RO, R/W
D8h–dBh Multiple USB3PR USB3 Port Routing 00000000h R/W, RO
DCh–DFh Core USB3PRM USB 3.0 Port Routing Mask 00000000h R/W, RO
E4h–E7h Multiple USB2PDO USB2 Port Disable Override 00000000h R/WO
E8h–EBh Multiple USB3PDO USB3 Port Disable Override 00000000h R/WO
Table 11-1. USB xHCI PCI Register Address Map (USB xHCI—D20:F0) (Sheet 2 of 2)
Offset
Power
Well
Mnemonic Register Name Default Value Type
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to Intel® Xeon® Processor D-1500 Product Family
USB xHCI controller.
Bit Description
15:11 Reserved
10 Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
The corresponding Interrupt Status bit (D20:F0, Offset 06h, bit 3) is not affected by the interrupt
enable.










