Datasheet
xHCI Controller Registers (D20:F0)
Intel® Xeon® Processor D-1500 Product Family 423
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
11 xHCI Controller Registers
(D20:F0)
11.1 USB xHCI Configuration Registers (USB xHCI—
D20:F0)
Note: Register address locations that are not shown in Table 11-1 should be treated as
Reserved (see Section 4.2 for details).
Note: “Multiple” in the Power Well column means that multiple power wells apply to this
register since the individual fields in the register may be on different power wells.
Table 11-1. USB xHCI PCI Register Address Map (USB xHCI—D20:F0) (Sheet 1 of 2)
Offset
Power
Well
Mnemonic Register Name Default Value Type
00h–01h Core VID Vendor Identification 8086h RO
02h–03h Core DID Device Identification See register
description
RO
04h–05h Core PCICMD PCI Command 0000h R/W, RO
06h–07h Core PCISTS PCI Status 0290h R/WC, RO
08h Core RID Revision Identification 00h RO
09h Core PI Programming Interface 30h RO
0Ah Core SCC Sub Class Code 03h RO
0Bh Core BCC Base Class Code 0Ch RO
0Dh Core PMLT Primary Master Latency Timer 00h RO
0Eh Core HEADTYP Header Type 00h RO
10h–13h Core MEM_BASE_L Memory Base Address Low 00000004h R/W, RO
14h–17h Core MEM_BASE_H Memory Base Address High 00000000h R/W
2Ch–2Dh Core SVID USB xHCI Subsystem Vendor
Identification
0000h R/W
2Eh–2Fh Core SID USB xHCI Subsystem Identification 0000h R/W
34h Core CAP_PTR Capabilities Pointer 70h RO
3Ch Core INT_LN Interrupt Line 00h R/W
3Dh Core INT_PN Interrupt Pin See register
description
RO
40h–43h Core XHCC xHC System Bus Configuration 0000F0FDh R/W, R/WC
44h–47h Multiple XHCC2 xHC System Bus Configuration 2 00000000h R/WO
60h Sus SBRN Serial Bus Release Number 30h RO
61h Multiple FL_ADJ Frame Length Adjustment 20h R/W
70h Core PWR_CAPID PCI Power Management Capability ID 01h RO
71h Core NXT_PTR1 Next Item Pointer #1 80h R/W
72h–73h Core PWR_CAP Power Management Capabilities C9C2h R/W, RO
74h–75h Multiple PWR_CNTL_STS Power Management Control / Status 0000h R/W, R/WC,
RO
80h Core MSI_CAPID Message Signaled Interrupt Capability
ID
05h RO