Datasheet

EHCI Controller Registers (D29:F0)

422 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

10.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register

Offset: MEM_BASE + A8h–AFh Attribute: R/W

Default Value: 0000000000000000h Size: 64 bits

This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.

10.2.3.4 CONFIG—Configuration Register

Offset: MEM_BASE + B0–B3h Attribute: R/W

Default Value: 00007F01h Size: 32 bits

15:8 SEND_PID_CNT[15:8] — R/W. Hardware sends this PID to begin the data packet when sending

data to USB (that is, WRITE_READ#_CNT is asserted). Software typically sets this field to either

DATA0 or DATA1 PID values.

7:0 TOKEN_PID_CNT[7:0] — R/W. Hardware sends this PID as the Token PID for each USB

transaction. Software typically sets this field to either IN, OUT, or SETUP PID values.

Bit Description

63:0 DATABUFFER[63:0] — R/W. This field is the 8 bytes of the data buffer. Bits 7:0 correspond to least

significant byte (byte 0). Bits 63:56 correspond to the most significant byte (byte 7).

The bytes in the Data Buffer must be written with data before software initiates a write request. For

a read request, the Data Buffer contains valid data when DONE_STS bit (offset A0, bit 16) is cleared

by the hardware, ERROR_GOOD#_STS (offset A0, bit 6) is cleared by the hardware, and the

DATA_LENGTH_CNT field (offset A0, bits 3:0) indicates the number of bytes that are valid.

Bit Description

31:15 Reserved

14:8 USB_ADDRESS_CNF — R/W. This 7-bit field identifies the USB device address used by the

controller for all Token PID generation. (Default = 7Fh)

7:4 Reserved

3:0 USB_ENDPOINT_CNF — R/W. This 4-bit field identifies the endpoint used by the controller for all

Token PID generation. (Default = 1h)