Datasheet

EHCI Controller Registers (D29:F0)
420 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.3 USB 2.0-Based Debug Port Registers
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F0:offset 5Ah). The specific EHCI port that supports
this debug capability (Port 1 for D29:F0) is indicated by a 4-bit field (bits 20–23) in the
HCSPARAMS register of the EHCI controller. The address map of the Debug Port
registers is shown in Tab le 1 0 - 4.
Notes:
1. All of these registers are implemented in the core well and reset by PLTRST#, EHC HCRESET, and a EHC
D3-to-D0 transition.
2. The hardware associated with this register provides no checks to ensure that software programs the
interface correctly. How the hardware behaves when programmed improperly is undefined.
10.2.3.1 CNTL_STS—Control / Status Register
Offset: MEM_BASE + A0h Attribute: R/W, R/WC, RO
Default Value: 00000000h Size: 32 bits
Power well: Suspend
0 Current Connect Status — RO. This value reflects the current state of the port, and may not
correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.
0 = No device is present. (Default)
1 = Device is present on port.
Bit Description
Table 10-4. Debug Port Register Address Map
MEM_BASE +
Offset
Mnemonic Register Name Default Attribute
A0–A3h CNTL_STS Control / Status 00000000h R/W, R/WC, RO
A4–A7h USBPID USB PIDs 00000000h R/W, RO
A8–AFh DATABUF[7:0] Data Buffer (Bytes 7:0) 00000000
00000000h
R/W
B0–B3h CONFIG Configuration 00007F01h R/W
Bit Description
31 Reserved
30 OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI controller (that is, immediately taken away
from the companion Classic USB Host controller) If the port was already owned by the EHCI
controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits
in the standard EHCI registers.
29 Reserved
28 ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same
conditions where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default)
1 = Debug port is enabled for operation. Software can directly set this bit if the port is already
enabled in the associated PORTSC register (this is enforced by the hardware).
27:17 Reserved
16 DONE_STS — R/WC. Software can clear this by writing a 1 to it.
0 = Request Not complete
1 = Set by hardware to indicate that the request is complete.
15:12 LINK_ID_STS — RO. This field identifies the link interface.
0h = Hardwired. Indicates that it is a USB Debug Port.