Datasheet

Intel® Xeon® Processor D-1500 Product Family and System Clocks
42 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2.5.1.8 SEPCICLKBP—Single Ended 33 MHz Clock Buffer Parameter Register
Attribute: R/W
Default Value: 00099999h Size: 32-bit
12 FLEX3 Clock Buffer Resistance Selection — R/W. This parameter controls Single/Double load series
resistance.
0 = 25 Ω single load usage
1 = 17 Ω double load usage (Default).
11:8 Reserved
7:5 FLEX1 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew rate of FLEX
clock 3. Each bit step change corresponds to ~0.2 V/ns.
000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
4 FLEX1 Clock Buffer Resistance Selection — R/W. This parameter controls Single/Double load series
resistance.
0 = 25Ω single load usage
1 = 17Ω double load usage (Default).
3:0 Reserved
Bit Description
Bit Description
31:20 Reserved
19:17 CLKOUT_33MHz_4 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew
rate of 33 MHz clock 4. Each bit step change corresponds to ~0.2 V/ns.
000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
16 CLKOUT_33MHz_4 Clock Buffer Resistance Selection — R/W. This parameter controls Single/
Double load series resistance.
0 = 25 Ω single load usage
1 = 17 Ω double load usage (Default).
15:13 CLKOUT_33MHz_3 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew
rate of 33 MHz clock 3. Each bit step change corresponds to ~0.2 V/ns.
000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
12 CLKOUT_33MHz_3 Clock Buffer Resistance Selection — R/W. This parameter controls Single/
Double load series resistance.
0 = 25 Ω single load usage
1 = 17 Ω double load usage (Default).
11:9 CLKOUT_33MHz_2 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew
rate of 33 MHz clock 2. Each bit step change corresponds to ~0.2 V/ns.
000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
8 CLKOUT_33MHz_2 Clock Buffer Resistance Selection — R/W. This parameter controls Single/
Double load series resistance.
0 = 25 Ω single load usage
1 = 17 Ω double load usage (Default).
7:5 CLKOUT_33MHz_1 Clock Buffer Slew Rate Selection — R/W. This parameter controls slew
rate of 33 MHz clock 1. Each bit step change corresponds to ~0.2 V/ns.
000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum