Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 419
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7 Suspend — R/W.
0 = Port not in suspend state.(Default)
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
When in suspend state, downstream propagation of data is blocked on this port, except for port
reset. The bit status does not change until the port is suspended and that there may be a delay in
suspending a port depending on the activity on the port.
The host controller will unconditionally set this bit to a 0 when software sets the Force Port Resume
bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller.
If host software sets this bit to a 1 when the port is not enabled (that is, Port enabled bit is a 0), the
results are undefined.
6 Force Port Resume — R/W.
0 = No resume (K-state) detected/driven on port. (Default)
1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The
Host controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a 1 because a
J-to-K transition is detected, the Port Change Detect bit (D29:F0:CAPLENGTH + 24h, bit 2) in
the USB2.0_STS register is also set to a 1. If software sets this bit to a 1, the host controller
must not set the Port Change Detect bit.
Note: When the EHCI controller owns the port, the resume sequence follows the defined sequence
documented in the USB Specification, Revision 2.0. The resume signaling (Full-speed 'K') is
driven on the port as long as this bit remains a 1. Software must appropriately time the
Resume and set this bit to a 0 when the appropriate amount of time has elapsed. Writing a 0
(from 1) causes the port to return to high-speed mode (forcing the bus below the port into a
high-speed idle). This bit will remain a 1 until the port has switched to the high-speed idle.
5 Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the port owner.
Software clears this bit by writing a 1 to it.
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
4 Overcurrent Active — RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0
when the over current condition is removed. Intel® Xeon® Processor D-1500 Product Family
automatically disables the port when the overcurrent active bit is 1.
3 Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only when a port is
disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB
Specification for the definition of a port error). This bit is not set due to the Disabled-to-Enabled
transition, nor due to a disconnect. Software clears this bit by writing a 1 to it.
0 = No change in status. (Default).
1 = Port enabled/disabled status has changed.
2 Port Enabled/Disabled — R/W. Ports can only be enabled by the host controller as a part of the
reset and enable. Software cannot enable a port by writing a 1 to this bit. Ports can be disabled by
either a fault condition (disconnect event or other fault condition) or by host software. The bit status
does not change until the port state actually changes. There may be a delay in disabling or enabling
a port due to other host controller and bus events.
0 = Disable
1 = Enable (Default)
1 Connect Status Change — R/WC. This bit indicates a change has occurred in the port’s Current
Connect Status. Software sets this bit to 0 by writing a 1 to it.
0 = No change (Default).
1 = Change in Current Connect Status. The host controller sets this bit for all changes to the port
device connect status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system software has cleared the
changed condition, hub hardware will be “setting” an already-set bit (that is, the bit will remain
set).
Bit Description
Port Enabled Suspend Port State
0XDisabled
10Enabled
11Suspend