Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 417
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.2.9 PORTSC—Port N Status and Control Register
Offset: Port 0 RMH: MEM_BASE + 64h–67h
Port 1 Debug Port: MEM_BASE + 68–6Bh
Port 2 USB redirect (if enabled): MEM_BASE + 6C–6Fh
Attribute: R/W, R/WC, RO
Default Value: 00003000h Size: 32 bits
Note: This register is associated with the upstream ports of the EHCI controller and does not
represent downstream hub ports. USB Hub class commands must be used to determine
RMH port status and enable test modes. See Chapter 11 of the USB Specification,
Revision 2.0 for more details. Rate Matching Hub wake capabilities can be configured
by the RMHWKCTL Register (RCBA+35B0h) located in the Chipset Configuration
chapter.
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
•Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI specification for operational requirements for how change events interact with
port suspend mode.
0 Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process of
configuring the Host controller. This bit controls the default port-routing control logic. Bit values and
side-effects are listed below. See Chapter 4 of the EHCI specification for operation details.
0 = Compatibility debug only (default).
1 = Port routing control logic default-routes all ports to this host controller.
Bit Description
Bit Description
31:23 Reserved
22 Wake on Overcurrent Enable (WKOC_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of
this register) is set.
21 Wake on Disconnect Enable (WKDSCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from connected to disconnected (that is, bit 0 of this register changes from 1 to 0).
20 Wake on Connect Enable (WKCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (that is, bit 0 of this register changes from 0 to 1).