Datasheet

EHCI Controller Registers (D29:F0)
416 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address Register
Offset: MEM_BASE + 34h–37h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since Intel® Xeon® Processor D-1500 Product Family host controller
operates in 64-bit mode (as indicated by the 1 in the 64-bit Addressing Capability field
in the HCCSPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of
every control data structure address comes from the CTRLDSSEGMENT register. HCD
loads this register prior to starting the schedule execution by the host controller. The
memory structure referenced by this physical memory pointer is assumed to be 4-
Kbyte aligned. The contents of this register are combined with the Frame Index
Register (FRINDEX) to enable the Host controller to step through the Periodic Frame
List in sequence.
10.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address Register
Offset: MEM_BASE + 38h–3Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since Intel® Xeon® Processor D-1500 Product Family host controller
operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing Capability field in the
HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits of every
control data structure address comes from the CTRLDSSEGMENT register (offset 08h).
Bits [4:0] of this register cannot be modified by system software and will always return
0s when read. The memory structure referenced by this physical memory pointer is
assumed to be 32-byte aligned.
10.2.2.8 CONFIGFLAG—Configure Flag Register
Offset: MEM_BASE + 60h–63h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset.
11:0 Upper Address[43:32] — R/W. This 12-bit field corresponds to address bits 43:32 when forming a
control data structure address.
Bit Description
Bit Description
31:12 Base Address (Low) — R/W. These bits correspond to memory address signals 31:12, respectively.
11:0 Reserved
Bit Description
31:5 Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals 31:5,
respectively. This field may only reference a Queue Head (QH).
4:0 Reserved
Bit Description
31:1 Reserved