Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 415
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.2.4 FRINDEX—Frame Index Register
Offset: MEM_BASE + 2Ch–2Fh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Refer to Section 4 of the EHCI specification for a detailed explanation
of the SOF value management requirements on the host controller. The value of
FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value. The
SOF value may be implemented as an 11-bit shadow register. For this discussion, this
shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames
(1 millisecond). An example implementation to achieve this behavior is to increment
SOFV each time the FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for high-speed isochronous scheduling purposes and to provide the get micro-
frame number function required to client drivers. Therefore, the value of FRINDEX and
the value of SOFV must be kept consistent if chip is reset or software writes to
FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to
SOFV[10:0]. In order to keep the update as simple as possible, software should never
write a FRINDEX value where the three least significant bits are 111b or 000b.
Note: This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for Intel® Xeon®
Processor D-1500 Product Family since it only supports 1024-entry frame lists. This
register must be written as a DWord. Word and byte writes produce undefined results.
This register cannot be written unless the Host controller is in the Halted state as
indicated by the HCHalted bit (D29:F0:CAPLENGTH + 24h, bit 12). A write to this
register while the Run/Stop bit (D29:F0:CAPLENGTH + 20h, bit 0) is set to a 1
(USB2.0_CMD register) produces undefined results. Writes to this register also effect
the SOF value. See Section 4 of the EHCI specification for details.
10.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment Register
Offset: MEM_BASE + 30h–33h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since Intel® Xeon® Processor D-1500 Product Family hardwires
the 64-bit Addressing Capability field in HCCPARAMS to 1, this register is used with the
link pointers to construct 64-bit addresses to EHCI control data structures. This register
is concatenated with the link pointer from either the PERIODICLISTBASE,
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures within the
same 4 GB memory segment.
Bit Description
31:14 Reserved
13:0 Frame List Current Index/Frame Number — R/W. The value in this register increments at the
end of each time frame (such as, micro-frame).
Bits [12:3] are used for the Frame List current index. This means that each location of the frame list
is accessed 8 times (frames or micro-frames) before moving to the next index.
Bit Description
31:12 Upper Address[63:44] — RO. Hardwired to 0s. Intel® Xeon® Processor D-1500 Product Family EHC
is only capable of generating addresses up to 16 terabytes (44 bits of address).