Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 413
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit Description
31:16 Reserved
15 Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the Asynchronous
Schedule.
0 = Disabled. (Default)
1 = Enabled.
Note: The Host controller is not required to immediately disable or enable the Asynchronous
Schedule when software transitions the Asynchronous Schedule Enable bit
(D29:F0:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either
enabled (1) or disabled (0).
14 Periodic Schedule Status ⎯ RO. This bit reports the current real status of the Periodic Schedule.
0 = Disabled. (Default)
1 = Enabled.
Note: The Host controller is not required to immediately disable or enable the Periodic Schedule
when software transitions the Periodic Schedule Enable bit (D29:F0:CAPLENGTH + 20h, bit
4) in the USB2.0_CMD register. When this bit and the Periodic Schedule Enable bit are the
same value, the Periodic Schedule is either enabled (1) or disabled (0).
13 Reclamation ⎯ RO. This read-only status bit is used to detect an empty asynchronous schedule. The
operational model and valid transitions for this bit are described in Section 4 of the EHCI
Specification.
12 HCHalted ⎯ RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit
being cleared to 0, either by software or by the Host controller hardware (such as, internal
error). (Default)
11:6 Reserved
5 Interrupt on Async Advance — R/WC. System software can force the host controller to issue an
interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to the
Interrupt on Async Advance Doorbell bit (D29:F0:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD
register. This bit indicates the assertion of that interrupt source.
4 Host System Error — R/WC.
0 = No serious error occurred during a host system access involving the Host controller module
1 = The Host controller sets this bit to 1 when a serious error occurs during a host system access
involving the Host controller module. A hardware interrupt is generated to the system. Memory
read cycles initiated by the EHC that receive any status other than Successful will result in this
bit being set.
When this error occurs, the Host controller clears the Run/Stop bit in the USB2.0_CMDregister
(D29:F0:CAPLENGTH + 20h, bit 0) to prevent further execution of the scheduled TDs. A
hardware interrupt is generated to the system (if enabled in the Interrupt Enable Register).
3 Frame List Rollover — R/WC.
0 = No Frame List Index rollover from its maximum value to 0.
1 = The Host controller sets this bit to a 1 when the Frame List Index rolls over from its maximum
value to 0. Since Intel® Xeon® Processor D-1500 Product Family only supports the 1024-entry
Frame List Size, the Frame List Index rolls over every time FRNUM13 toggles.
2 Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary power well.
Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is
loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent
change, enable/disable change and connect status change). Regardless of the implementation, when
this bit is readable (that is, in the D0 state), it must provide a valid view of the Port Status registers.
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port.
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is cleared to 0
has a change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port.
1 USB Error Interrupt (USBERRINT) — R/WC.
0 = No error condition.
1 = The Host controller sets this bit to 1 when completion of a USB transaction results in an error
condition (such as, error counter underflow). If the TD on which the error interrupt occurred also
had its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a list of the USB
errors that will result in this interrupt being asserted.