Datasheet

EHCI Controller Registers (D29:F0)
412 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: The Command Register indicates the command to be executed by the serial bus host controller. Writing
to the register causes a command to be executed.
10.2.2.2 USB2.0_STS—USB 2.0 Status Register
Offset: MEM_BASE + 24h–27h Attribute: R/WC, RO
Default Value: 00001000h Size: 32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
4 Periodic Schedule Enable — R/W. This bit controls whether the host controller skips processing
the Periodic Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
3:2 Frame List Size — RO. This field is R/W only if Programmable Frame List Flag in the HCCPARAMS
registers is set to a one. This field specifies the size of the frame list.
00b = 1024 elements (4096 bytes) - Default value
01b = 512 elements (2048 bytes)
10b = 256 elements (1024 bytes) for resource constrained environments.
1 Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset the host
controller. The effects of this on root hub registers are similar to a Chip Hardware Reset (that is,
RSMRST# assertion and PWROK de-assertion on Intel® Xeon® Processor D-1500 Product Family ).
When software writes a 1 to this bit, the host controller resets its internal pipelines, timers, counters,
state machines, and so on to their initial value. Any transaction currently in progress on USB is
immediately terminated. A USB reset is not driven on downstream ports.
Note: PCI configuration registers and Host controller capability registers are not effected by this
reset.
All operational registers, including port registers and port state machines are set to their initial
values. Port ownership reverts to the companion host controller(s), with the side effects described in
the EHCI specification. Software must re-initialize the host controller in order to return the host
controller to an operational state.
This bit is cleared to 0 by the host controller when the reset process is complete. Software cannot
terminate the reset process early by writing a 0 to this register.
Software should not set this bit to a 1 when the HCHalted bit (D29:F0:CAPLENGTH + 24h, bit 12) in
the USB2.0_STS register is a 0. Attempting to reset an actively running host controller will result in
undefined behavior. This reset me be used to leave EHCI port test modes.
0 Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule. The Host
controller continues execution as long as this bit is set. When this bit is cleared to 0, the Host
controller completes the current transaction on the USB and then halts. The HCHalted bit in the
USB2.0_STS register indicates when the Host controller has finished the transaction and has
entered the stopped state.
Software should not write a 1 to this field unless the host controller is in the Halted state (that is,
HCHalted in the USBSTS register is a 1). The Halted bit is cleared immediately when the Run bit is
set.
The following table explains how the different combinations of Run and Halted should be interpreted:
Memory read cycles initiated by the EHC that receive any status other than Successful will result in
this bit being cleared.
Bit Description
Run/Stop Halted Interpretation
0b 0b In the process of halting
0b 1b Halted
1b 0b Running
1b 1b Invalid – the HCHalted bit clears immediately