Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 411
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
• Suspend well hardware reset
• HCRESET
10.2.2.1 USB2.0_CMD—USB 2.0 Command Register
Offset: MEM_BASE + 20–23h Attribute: R/W, RO
Default Value: 00080000h Size: 32 bits
Bit Description
31:24 Reserved
23:16 Interrupt Threshold Control — R/W. System software uses this field to select the maximum rate
at which the host controller will issue interrupts. The only valid values are defined below. If software
writes an invalid value to this register, the results are undefined.
15:14 Reserved
13 Asynch Schedule Update (ASC) — R/W. This bit is used by the EHCI Asycnh schedule caching
function.when operating in C0 mode. it is ignored when Asynch caching operates in Cx mode. When
this bit is set, it allows the asynch schedule to be cached. When cleared, it causes the cache to be
disabled and all modified entries to be written back.
12 Periodic Schedule Prefetch Enable — R/W. This bit is used by software to enable the host
controller to prefetch the periodic schedule even in C0.
0 = Pre-fetch based pause enabled only when not in C0.
1 = Pre-fetch based pause enable in C0.
Once software has written a 1b to this bit to enable periodic schedule prefetching, it must disable
prefetching by writing a 0b to this bit whenever periodic schedule updates are about to begin.
Software should continue to dynamically disable and re-enable the prefetcher surrounding any
updates to the periodic scheduler (that is, until the host controller has been reset using a HCRESET).
11:8 Unimplemented Asynchronous Park Mode Bits — RO. Hardwired to 000b indicating the host
controller does not support this optional feature.
7 Light Host Controller Reset — RO. Hardwired to 0. Intel® Xeon® Processor D-1500 Product Family
does not implement this optional reset.
6 Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by software to tell the
host controller to issue an interrupt the next time it advances asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit
(D29:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register to a 1.
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all
appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the
USB2.0_STS register. If the Interrupt on Async Advance Enable bit in the USB2.0_INTR register
(D29:F0:CAPLENGTH + 28h, bit 5) is a 1 then the host controller will assert an interrupt at the
next interrupt threshold. See the EHCI specification for operational details.
Note: Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing
so will yield undefined results.
5 Asynchronous Schedule Enable — R/W. This bit controls whether the host controller skips
processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Value Maximum Interrupt Interval
00h Reserved
01h 1 micro-frame
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (default, equates to 1 ms)
10h 16 micro-frames (2 ms)
20h 32 micro-frames (4 ms)
40h 64 micro-frames (8 ms)