Datasheet

EHCI Controller Registers (D29:F0)
410 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities registers. The operational register base must be
DWord-aligned and is calculated by adding the value in the first capabilities register
(CAPLENGTH) to the base address of the enhanced host controller register address
space (MEM_BASE). Since CAPLENGTH is always 20h, Tab l e 1 0-3 already accounts for
this offset. All registers are 32 bits in length.
Note: Software must read and write these registers using only DWord accesses.These
registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
• Core well hardware reset
• HCRESET
•D3-to-D0 reset
3Reserved
2 Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating that the host
controller does not support this optional feature
1 Programmable Frame List Flag — RO.
0 = System software must use a frame list length of 1024 elements with this host controller. The
USB2.0_CMD register (D29:F0:CAPLENGTH + 20h, bits 3:2) Frame List Size field is a read-only
register and must be cleared to 0.
1 = System software can specify and use a smaller frame list and configure the host controller using
the USB2.0_CMD register Frame List Size field. The frame list must always be aligned on a 4K
page boundary. This requirement ensures that the frame list is always physically contiguous.
0 64-bit Addressing Capability — RO. This field documents the addressing range capability of this
implementation. The value of this field determines whether software should use the 32-bit or 64-bit
data structures.
This bit is hardwired to 1.
Note: Intel® Xeon® Processor D-1500 Product Family supports 64 bit addressing only.
Bit Description
Table 10-3. Enhanced Host Controller Operational Register Address Map
MEM_BASE
+ Offset
Mnemonic Register Name Default
Special
Notes
Attribute
20h–23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO
24h–27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO
28h–2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W, RO
2Ch–2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W, RO
30h–33h CTRLDSSEGMENT Control Data Structure Segment 00000000h R/W, RO
34h–37h PERIODICLISTBASE Periodic Frame List Base Address 00000000h R/W, RO
38h–3Bh ASYNCLISTADDR Current Asynchronous List Address 00000000h R/W, RO
3Ch–5Fh — Reserved 0h RO
60h–63h CONFIGFLAG Configure Flag 00000000h Suspend R/W, RO
64h–67h PORT1SC Port 1 Status and Control 00003000h Suspend R/W, R/WC, RO
68h–6Bh PORT2SC Port 2 Status and Control 00003000h Suspend R/W, R/WC, RO
6Ch–6Fh PORT3SC Port 3 Status and Control 00003000h Suspend R/W, R/WC, RO
A0h–B3h — Debug Port Registers Undefined R/W, RO
B4h–3FFh — Reserved Undefined RO