Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 409
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.2.1.2 HCIVERSION—Host Controller Interface Version Number Register
Offset: MEM_BASE + 02h–03h Attribute: RO
Default Value: 0100h Size: 16 bits
10.2.1.3 HCSPARAMS—Host Controller Structural Parameters
Offset: MEM_BASE + 04h–07h Attribute: R/W, RO
Default Value: 00200008h (D29:F0) Size: 32 bits
00200006h (D26:F0)
Function Level Reset: No
Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.
Note: This register is writable when the WRT_RDONLY bit is set.
10.2.1.4 HCCPARAMS—Host Controller Capability Parameters Register
Offset: MEM_BASE + 08h–0Bh Attribute: R/W, RO
Default Value: 00036881h Size: 32 bits
Bit Description
15:0 Host Controller Interface Version Number — RO. This is a two-byte register containing a BCD
encoding of the version number of interface that this host controller interface conforms.
Bit Description
31:24 Reserved
23:20 Debug Port Number (DP_N) — RO. Hardwired to 2h indicating that the Debug Port is on the
second lowest numbered port on the EHCI.
EHCI#1: Port 1
19:16 Reserved
15:12 Number of Companion Controllers (N_CC) — RO. This field indicates the number of companion
controllers associated with this USB EHCI host controller.There are no companion controllers so this
field is set to zero as a read only bit.
11:8 Number of Ports per Companion Controller (N_PCC) — RO. This field indicates the number of
ports supported per companion host controller. This field is 0h indication no other companion
controller support.
7:4 Reserved. These bits are reserved and default to 0.
3:0 N_PORTS — R/W. This field specifies the number of physical downstream ports implemented on this
host controller. The value of this field determines how many port registers are addressable in the
Operational Register Space. Valid values are in the range of 1h to Fh. A 0 in this field is undefined.
For Integrated USB 2.0 Rate Matching Hub Enabled: Each EHCI reports 2 ports by default. Port 0
assigned to the RMH and port 1 assigned as the debug port. When the KVM/USB-R feature is enabled
it will show up as Port2 on the EHCI, and BIOS would need to update this field to 3h.
Bit Description
31:18 Reserved
17 Asynchronous Schedule Update Capability (ASUC) — R/W. This bit indicates that the hardware
supports the Asynch schedule prefetch enable bit in the USB command register.
16 Periodic Schedule Update Capability (PSUC) — R/W. This field indicates that the EHC hardware
supports the Periodic Schedule prefetch bit in the USB2.0_CMD register.
15:8 EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h, indicating that
the EHCI capabilities list exists and begins at offset 68h in the PCI configuration space.
7:4 Isochronous Scheduling Threshold — R/W. This field indicates, relative to the current position of
the executing host controller, where software can reliably update the isochronous schedule. When bit
7 is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller
hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1,
then host software assumes the host controller may cache an isochronous data structure for an
entire frame. Refer to the EHCI specification for details on how software uses this information for
scheduling isochronous transfers.
This field is hardwired to 8h.