Datasheet
EHCI Controller Registers (D29:F0)
408 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F0:04h, bit 1) is not set in the Command register in configuration
space, the memory range will not be decoded by Intel® Xeon® Processor D-1500
Product Family enhanced host controller (EHC). If the MSE bit is not set, Intel® Xeon®
Processor D-1500 Product Family must default to allowing any memory accesses for
the range specified in the BAR to go to PCI. This is because the range may not be valid
and, therefore, the cycle must be made available to any other targets that may be
currently using that range.
10.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural
parameters register is writable. These registers are implemented in the suspend well
and is only reset by the standard suspend-well hardware reset, not by HCRESET or the
D3-to-D0 reset.
Note: The EHCI controller does not support as a target memory transactions that are locked
transactions. Attempting to access the EHCI controller Memory-Mapped I/O space
using locked memory transactions will result in undefined behavior.
Note: When the USB2 function is in the D3 PCI power state, accesses to the USB2 memory
range are ignored and will result in a master abort. Similarly, if the Memory Space
Enable (MSE) bit is not set in the Command register in configuration space, the
memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE
bit is not set, the EHC will not claim any memory accesses for the range specified in the
BAR.
Note: “Read/Write Special” means that the register is normally read-only, but may be written when the
WRT_RDONLY bit is set. Because these registers are expected to be programmed by BIOS during
initialization, their contents must not get modified by HCRESET or D3-to-D0 internal reset.
10.2.1.1 CAPLENGTH—Capability Registers Length Register
Offset: MEM_BASE + 00h Attribute: RO
Default Value: 20h Size: 8 bits
Table 10-2. Enhanced Host Controller Capability Registers
MEM_BASE +
Offset
Mnemonic Register Default Attribute
00h CAPLENGTH Capabilities Registers Length 20h RO
02h–03h HCIVERSION Host Controller Interface Version Number 0100h RO
04h–07h HCSPARAMS Host Controller Structural Parameters 00204208h
(D29:F0)
00203206
(D26:F0)
R/W (special),
RO
08h–0Bh HCCPARAMS Host Controller Capability Parameters 0003688h R/W, RO
Bit Description
7:0 Capability Register Length Value — RO. This register is used as an offset to add to the Memory
Base Register (D29:F0:10h) to find the beginning of the Operational Register Space. This field is
hardwired to 20h indicating that the Operation Registers begin at offset 20h.