Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 407
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.38 FLR_CLV—Function Level Reset Capability Length and
Version Register (USB EHCI—D29:F0)
Address Offset: 9Ah–9Bh Attribute: R/WO, RO
Default Value: 0306h Size: 16 bits
Function Level Reset: No
When FLRCSSEL = 0, this register is defined as follows:
10.1.39 FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0)
Address Offset: 9Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
10.1.40 FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0)
Address Offset: 9Dh Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
10.2 Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers—Capability
Registers and Operational Registers.
Note: Intel® Xeon® Processor D-1500 Product Family EHCI controller will not accept
memory transactions (neither reads nor writes) as a target that are locked
transactions. The locked transactions should not be forwarded to PCI as the address
space is known to be allocated to USB.
Bit Description
15:10 Reserved
9 FLR Capability — R/WO.
1 = Support for Function Level Reset (FLR).
8 TXP Capability — R/WO.
1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is supported.
7:0 Capability Length — RO. This field indicates the # of bytes of this vendor specific capability as
required by the PCI specification. It has the value of 06h for the FLR capability.
Bit Description
7:1 Reserved
0 Initiate FLR — R/W. This bit is used to initiate FLR transition. A write of 1 initiates FLR transition.
Since hardware must not respond to any cycles until FLR completion, the value read by software
from this bit is always 0.
Bit Description
7:1 Reserved
0 Transactions Pending (TXP) — RO.
0 = Completions for all non-posted requests have been received.
1 = Controller has issued non-posted requests which have not been completed.