Datasheet

EHCI Controller Registers (D29:F0)
406 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.35 EHCIIR1—EHCI Initialization Register 1 (USB EHCI—
D29:F0)
Address Offset: 84h Attribute: R/W
Default Value: 01h Size: 32 bits
Power well: Core
10.1.36 FLR_CID—Function Level Reset Capability ID Register
(USB EHCI—D29:F0)
Address Offset: 98h Attribute: RO
Default Value: 13h Size: 8 bits
Function Level Reset: No
10.1.37 FLR_NEXT—Function Level Reset Next Capability Pointer
Register (USB EHCI—D29:F0)
Address Offset: 99h Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
0 WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-only
registers in the EHC function to be written by software. Registers that may only be written
when this mode is entered are noted in the summary tables and detailed description as
“Read/Write-Special”. The registers fall into two categories:
1. System-configured parameters
2. Status bits
Bit Description
Bit Description
31:29 Reserved
28 EHCI Prefetch Entry Clear — R/W.
0 = EHC will clear prefetched entries in DMA.
1 = EHC will not clear prefetched entries in DMA
27:5 Reserved
4 Intel
®
Pre-fetch Based Pause Enable — R/W.
0 = Intel Pre-fetch Based Pause is disabled.
1 = Intel Pre-fetch Based Pause is enabled.
3:0 Reserved
Bit Description
7:0 Capability ID — RO.
13h = Capability ID
Bit Description
7:0 A value of 00h in this register indicates this is the last capability field.