Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 403
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.31 SPECIAL_SMI—Intel
®
Specific USB 2.0 SMI Register
(USB EHCI—D29:F0)
Address Offset: 70h–73h Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
5 SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F0:6Ch, bit 21) is a 1, the
host controller will issue an SMI immediately.
4 SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F0:6Ch, bit 20) is a 1, the
host controller will issue an SMI.
3 SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F0:6Ch, bit 19) is a 1,
the host controller will issue an SMI.
2 SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F0:6Ch, bit 18) is a 1,
the host controller will issue an SMI.
1 SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F0:6Ch, bit 17) is a 1, the host
controller will issue an SMI immediately.
0 SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F0:6Ch, bit 16) is a 1, the
host controller will issue an SMI immediately.
Bit Description
Bit Description
31:25 Reserved
24:22 SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 24:22 correspond to the Port Owner bits for ports 0 (22) through 3 (24). These bits
are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0.
21 SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
0 = Power State bits Not modified.
1 = Software modified the Power State bits in the Power Management Control/Status
(PMCSR) register (D29:F0:54h).
20 SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
19 SMI on Periodic — R/WC. Software clears this bit by writing a 1 it.
0 = No Periodic Schedule Enable bit change.
1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.
18 SMI on CF — R/WC. Software clears this bit by writing a 1 it.
0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
17 SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.
0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared).
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).