Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 401
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.27 PDO—Port Disable Override Register
Address Offset: 64h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Power Well: Suspend
10.1.28 RMHDEVR—RMH Device Removable Field Register
Address Offset: 66h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Power Well: Suspend
10.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F0)
Address Offset: 68–6Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
15:8 Reserved, Read Only
7:0 USB Port Disable: A ‘1’ in a bit position prevents the corresponding USB port from reporting a
Device Connection to the hub. Attempts to enable the port will be ignored by the hardware
when this bit is 1.
This register cannot be written when the USB Per-Port Registers Write Enable bit (in Power
Management I/O Space) is 0.
Bit Description
15:9 Reserved, Read Only
8:1 Device Removable Bit Map: A ‘1’ in a given bit position in this field indicates that the
corresponding downstream port of the RMH is connected to a non-removable device. A ‘0’
indicates that the port is exposed to the user.
Bits 8:1 are mapped to Ports 8:1 (on EHCI #1, Device. 29)
This bits control the value returned by the RMH in the Deviceremovable field of the Hub
Descriptor. A ‘1’ in a given bit position in this register will result in the corresponding bit in the
DeviceRemovable field of the hub descriptor being set to ‘1’ as well (indicating that the port is
connected to a non-removable device).
System BIOS is expected to set these values upon Boot and resume from Sx states.
Note: Bits 8:5 are reserved (maintained as RW but with no significance) for since RMH
corresponding to EHCI has only 4 ports.
0 Reserved, Read Only
Bit Description
31:25 Reserved — RO. Hardwired to 00h
24 HC OS Owned Semaphore — R/W. System software sets this bit to request ownership of the EHCI
controller. Ownership is obtained when this bit reads as 1 and the HC BIOS Owned Semaphore bit
reads as clear.
23:17 Reserved — RO. Hardwired to 00h
16 HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of the EHCI
controller. System BIOS will clear this bit in response to a request for ownership of the EHCI
controller by system software.
15:8 Next EHCI Capability Pointer — RO. Hardwired to 00h to indicate that there are no EHCI
Extended Capability structures in this device.
7:0 Capability ID — RO. Hardwired to 01h to indicate that this EHCI Extended Capability is the Legacy
Support Capability.