Datasheet

EHCI Controller Registers (D29:F0)
400 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
is operating yields undefined results. It should not be reprogrammed by USB system
software unless the default or BIOS programmed values are incorrect, or the system is
restoring the register while returning from a suspended state.
These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.
10.1.26 PWAKE_CAP—Port Wake Capability Register (USB EHCI—
D29:F0)
Address Offset: 62–63h Attribute: R/W, RO
Default Value: 07FFh Size: 16 bits
Function Level Reset: No Power Well: Suspend
This register is in the suspend power well. The intended use of this register is to
establish a policy about which ports are to be used for wake events. Bit positions 1–
8(D29)in the mask correspond to a physical port implemented on the current EHCI
controller. A 1 in a bit position indicates that a device connected below the port can be
enabled as a wake-up device and the port may be enabled for disconnect/connect or
overcurrent events as wake-up events. This is an information-only mask register. The
bits in this register do not affect the actual operation of the EHCI host controller. The
system-specific policy can be established by BIOS initializing this register to a system-
specific value. System software uses the information in this register when enabling
devices and ports for remote wake-up.
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
s
Bit Description
7:6 Reserved — RO. These bits are reserved for future use and should read as 00b.
5:0 Frame Length Timing Value — R/W. Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF
micro-frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h)
that gives a SOF cycle time of 60000.
Frame Length (# 480 MHz Clocks)
(decimal)
Frame Length Timing Value (this register)
(decimal)
59488 0
59504 1
59520 2
——
59984 31
60000 32
——
60480 62
60496 63
Bit Description
15:11 Reserved, Read Only
10:1 (D29) Port Wake Up Capability Mask — R/W. Bit positions 1-10 correspond to a physical port
implemented on this host controller. For example, bit position 1 corresponds to port 1, bit
position 2 corresponds to port 2, and so on.
0 Port Wake Implemented — R/W. A 1 in this bit indicates that this register is implemented to
software.