Datasheet

Intel® Xeon® Processor D-1500 Product Family and System Clocks
40 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2.5.1.5 DIV_FLEX4824—48 MHz and 24 MHz Single Ended FLEX Clock Divide
Enable Register
Attribute: R/W
Default Value: 00030103h Size: 32-bit
2.5.1.6 OCKEN—Output Clock Enable Register
Attribute: R/W
Default Value: 7DFF0F8Fh Size: 32-bit
Bit Description
31:16 Reserved
15 DIV_FLEX4824 Enable/Disable — R/W. This register controls the 48 MHz and 24 MHz single
ended FLEX clock divider from a 96 MHz internal clock source.
0 = Enables divider
1 = Disables divider
14:11 Reserved
10:8 DIV_FLEX4824 Divider Selection — R/W.
001 = Enables a divide by 2 from an internal 96 MHz clock source for 48 MHz single ended clock
FLEX clock output frequency. (Default)
100 = Enables a divide by 4 from an internal 96 MHz clock source for a 24 MHz single ended clock
FLEX clock output frequency.
All other values are not supported.
7:0 Reserved
Bit Description
31 Reserved
30 DPNS Clock Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
Note: This clock must be connected to the processor (and functional) regardless of internal
graphics configuration support.
29 DP Clock Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
28 Reserved
27 PEG_B Clock Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
26 PEG_A Clock Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
25 Reserved
24 ITPXDP Clock Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
23 PCIe* Clock 7 Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
22 PCIe Clock 6 Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
21 PCIe Clock 5 Output Clock Enable — R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).