Datasheet
4 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.10 Serial Interrupt (D31:F0)........................................................................................... 85
3.10.1 Start Frame ................................................................................................. 86
3.10.2 Data Frames ................................................................................................ 86
3.10.3 Stop Frame.................................................................................................. 87
3.10.4 Specific Interrupts Not Supported Using SERIRQ ............................................... 87
3.10.5 Data Frame Format....................................................................................... 87
3.11 Real Time Clock (D31:F0).......................................................................................... 88
3.11.1 Update Cycles .............................................................................................. 89
3.11.2 Interrupts .................................................................................................... 89
3.11.3 Lockable RAM Ranges.................................................................................... 89
3.11.4 Century Rollover........................................................................................... 89
3.11.5 Clearing Battery-Backed RTC RAM................................................................... 90
3.12 Power Management .................................................................................................. 91
3.12.1 Features ...................................................................................................... 91
3.12.2 Intel® Xeon® Processor D-1500 Product Family and System Power
States ......................................................................................................... 92
3.12.3 System Power Planes .................................................................................... 93
3.12.4 SMI# / SCI Generation .................................................................................. 94
3.12.5 C-States ...................................................................................................... 97
3.12.6 Sleep States ................................................................................................ 97
3.12.7 Event Input Signals and Their Usage ............................................................. 100
3.12.8 ALT Access Mode ........................................................................................ 103
3.12.9 System Power Supplies, Planes, and Signals................................................... 106
3.12.10 Legacy Power Management Theory of Operation ............................................. 110
3.12.11 Reset Behavior ........................................................................................... 110
3.13 System Management (D31:F0)................................................................................. 112
3.13.1 Theory of Operation .................................................................................... 112
3.13.2 TCO Modes ................................................................................................ 114
3.14 General Purpose I/O (D31:F0).................................................................................. 115
3.14.1 Power Wells ............................................................................................... 116
3.14.2 SMI# SCI and NMI Routing .......................................................................... 116
3.14.3 Triggering.................................................................................................. 116
3.14.4 GPIO Registers Lockdown ............................................................................ 116
3.14.5 Serial POST Codes over GPIO ....................................................................... 117
3.15 SATA Host Controller (D31:F2, F5) ........................................................................... 119
3.15.1 SATA 6 Gb/s Support .................................................................................. 120
3.15.2 SATA Feature Support ................................................................................. 120
3.15.3 Theory of Operation .................................................................................... 121
3.15.4 SATA Swap Bay Support .............................................................................. 121
3.15.5 Hot-Plug Operation ..................................................................................... 122
3.15.6 Function Level Reset Support (FLR)............................................................... 122
3.15.7 Power Management Operation ...................................................................... 122
3.15.8 SATA Device Presence ................................................................................. 124
3.15.9 SATA LED .................................................................................................. 125
3.15.10 AHCI Operation .......................................................................................... 125
3.15.11 SGPIO Signals ............................................................................................ 126
3.16 High Precision Event Timers (HPET) .......................................................................... 130
3.16.1 Timer Accuracy........................................................................................... 130
3.16.2 Interrupt Mapping....................................................................................... 130
3.16.3 Periodic versus Non-Periodic Modes............................................................... 131
3.16.4 Enabling the Timers .................................................................................... 132
3.16.5 Interrupt Levels.......................................................................................... 132
3.16.6 Handling Interrupts..................................................................................... 133
3.16.7 Issues Related to 64-Bit Timers with 32-Bit Processors .................................... 133
3.17 USB EHCI Host Controllers (D29:F0) ......................................................................... 133
3.17.1 EHC Initialization ........................................................................................ 134
3.17.2 Data Structures in Main Memory ................................................................... 134
3.17.3 USB 2.0 Enhanced Host Controller DMA ......................................................... 134
3.17.4 Data Encoding and Bit Stuffing ..................................................................... 135
3.17.5 Packet Formats........................................................................................... 135
3.17.6 USB 2.0 Interrupts and Error Conditions ........................................................ 135
3.17.7 USB 2.0 Power Management ........................................................................ 136
3.17.8 USB 2.0 Legacy Keyboard Operation ............................................................. 137
3.17.9 USB 2.0 Based Debug Port ........................................................................... 137
3.17.10 EHCI Caching ............................................................................................. 142
3.17.11 Intel
®
USB Pre-Fetch Based Pause ................................................................ 142