Datasheet

EHCI Controller Registers (D29:F0)
398 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. Normally, this register is read-only to report capabilities to the power management software. To report
different power management capabilities, depending on the system in which Intel® Xeon® Processor D-
1500 Product Family is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit
(D29:F0:80h, bit 0) is set. The value written to this register does not affect the hardware other than
changing the value returned during a read.
2. Reset: core well, but not D3-to-D0 warm reset.
10.1.20 PWR_CNTL_STS—Power Management Control / Status
Register (USB EHCI—D29:F0)
Address Offset: 54h–55h Attribute: R/W, R/WC, RO
Default Value: 0000h Size: 16 bits
Power Well Bits 1,0:Core; Power Well Bits 15,8: Suspend
Note: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
5 Device Specific Initialization (DSI)— RO. Intel® Xeon® Processor D-1500 Product Family
reports 0, indicating that no
device-specific initialization is required.
4 Reserved
3 PME Clock (PME_CLK) — RO. Intel® Xeon® Processor D-1500 Product Family reports 0,
indicating that no PCI clock is required to generate PME#.
2:0 Version (VER) — RO. Intel® Xeon® Processor D-1500 Product Family reports 010b, indicating that
it complies with Revision 1.1 of the PCI Power Management Specification.
Bit Description
Bit Description
15 PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to de-assert (if enabled).
1 = This bit is set when Intel® Xeon® Processor D-1500 Product Family EHC would normally assert
the PME# signal independent of the state of the PME_En bit.
Note: This bit must be explicitly cleared by the operating system each time the operating system
is loaded.
This bit is not reset by Function Level Reset.
14:13 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data register.
12:9 Data Select — RO. Hardwired to 0000b indicating it does not support the associated Data register.
8 PME Enable — R/W.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family EHC to generate an internal PME
signal when PME_Status is 1.
Note: This bit must be explicitly cleared by the operating system each time it is initially loaded.
This bit is not reset by Function Level Reset.
7:2 Reserved
1:0 Power State — R/W. This 2-bit field is used both to determine the current power state of EHC
function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3
HOT
state
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs. When in the D3
HOT
state,
Intel® Xeon® Processor D-1500 Product Family must not accept accesses to the EHC memory
range; but the configuration space must still be accessible. When not in the D0 state, the generation
of the interrupt output is blocked. Specifically, the PIRQH is not asserted by Intel® Xeon® Processor
D-1500 Product Family when not in the D0 state.
When software changes this value from the D3
HOT
state to the D0 state, an internal warm (soft)
reset is generated, and software must re-initialize the function.