Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 397
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.16 INT_PN—Interrupt Pin Register (USB EHCI—D29:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
10.1.17 PWR_CAPID—PCI Power Management Capability
Identification Register (USB EHCI—D29:F0)
Address Offset: 50h Attribute: RO
Default Value: 01h Size: 8 bits
10.1.18 NXT_PTR1—Next Item Pointer #1 Register (USB EHCI—
D29:F0)
Address Offset: 51h Attribute: R/W
Default Value: 58h Size: 8 bits
Power Well: Core
10.1.19 PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0)
Address Offset: 52h–53h Attribute: R/W, RO
Default Value: C9C2h Size: 16 bits
Power Well: Core
Bit Description
7:0 Interrupt Pin — RO. This reflects the value of D29IP.E1IP (Chipset Config Registers:Offset
3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset 3114:bits 3:0).
Note: As a single function device, only INTA# may be used while the other three interrupt lines
have no meaning. (refer to PCI 3.0 specification, Section 2.2.6, Interrupt Pins).
Note: Bits 7:4 are always 0h
Bit Description
7:0 Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.
Bit Description
7:0 Next Item Pointer 1 Value — R/W (special). This register defaults to 58h that indicates that the
next capability registers begin at configuration offset 58h. This register is writable when the
WRT_RDONLY bit (D29:F0:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port
capability registers, if necessary. This register should only be written during system initialization
before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h
(Debug Port and FLR capabilities visible) and 98h (Debug Port invisible, next capability is FLR) are
expected to be programmed in this register.
Note: Register not reset by D3-to-D0 warm reset.
Bit Description
15:11 PME Support (PME_SUP) — R/W. This 5-bit field indicates the power states in which the function
may assert PME#. Intel® Xeon® Processor D-1500 Product Family EHC does not support the D1 or
D2 states. For all other states, Intel® Xeon® Processor D-1500 Product Family EHC is capable of
generating PME#. Software should never need to modify this field.
10 D2 Support (D2_SUP) — RO.
0 = D2 State is not supported
9 D1 Support (D1_SUP) — RO.
0 = D1 State is not supported
8:6 Auxiliary Current (AUX_CUR) — R/W. Intel® Xeon® Processor D-1500 Product Family EHC
reports 375 mA maximum suspend well current required when in the D3
COLD
state.