Datasheet

EHCI Controller Registers (D29:F0)
396 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.12 SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F0)
Address Offset: 2Ch–2Dh Attribute: R/W
Default Value: XXXXh Size: 16 bits
Reset: None Power Well: Core
10.1.13 SID—USB EHCI Subsystem ID Register (USB EHCI—
D29:F0)
Address Offset: 2Eh–2Fh Attribute: R/W
Default Value: XXXXh Size: 16 bits
Reset: None Power Well: Core
10.1.14 CAP_PTR—Capabilities Pointer Register (USB EHCI—
D29:F0)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
Power Well: Core
10.1.15 INT_LN—Interrupt Line Register (USB EHCI—D29:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Reset: No Power Well: Core
Bit Description
15:0 Subsystem Vendor ID (SVID) — R/W. This register, in combination with the USB 2.0 Subsystem
ID register, enables the operating system to distinguish each subsystem from the others.
Note: Writes to this register are enabled when the WRT_RDONLY bit (D29:F0:80h, bit 0) is set
to 1.
Bit Description
15:0 Subsystem ID (SID) — R/W. BIOS sets the value in this register to identify the Subsystem ID. This
register, in combination with the Subsystem Vendor ID register, enables the operating system to
distinguish each subsystem from other(s).
Note: Writes to this register are enabled when the WRT_RDONLY bit (D29:F0:80h, bit 0) is set
to 1.
Bit Description
7:0 Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the USB 2.0
capabilities ranges.
Bit Description
7:0 Interrupt Line (INT_LN) — R/W. This data is not used by Intel® Xeon® Processor D-1500 Product
Family . It is used as a scratchpad register to communicate to software the interrupt line that the
interrupt pin is connected to.