Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 395
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.8 BCC—Base Class Code Register (USB EHCI—D29:F0)
Address Offset: 0Bh Attribute: RO
Default Value: 0Ch Size: 8 bits
10.1.9 PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
10.1.10 HEADTYP—Header Type Register (USB EHCI—D29:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
10.1.11 MEM_BASE—Memory Base Address Register (USB EHCI—
D29:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
7:0 Base Class Code (BCC) — RO.
0Ch = Serial bus controller.
Bit Description
7:0 Master Latency Timer Count (MLTC) — RO. Hardwired to 00h. Because the EHCI controller is
internally implemented with arbitration on an interface (and not PCI), it does not need a master
latency timer.
Bit Description
7 Multi-Function Device — RO. When set to ‘1’ indicates this is a multifunction device:
0 = Single-function device
1 = Multi-function device.
6:0 Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration layout.
Bit Description
31:10 Base Address — R/W. Bits [31:10] correspond to memory address signals [31:10], respectively.
This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
9:4 Reserved
3 Prefetchable — RO. Hardwired to 0 indicating that this range should not be prefetched.
2:1 Type — RO. Hardwired to 00b indicating that this range can be mapped anywhere within 32-bit
address space.
0 Resource Type Indicator (RTE) — RO. Hardwired to 0 indicating that the base address field in this
register maps to memory space.