Datasheet

EHCI Controller Registers (D29:F0)
394 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.5 RID—Revision Identification Register (USB EHCI—D29:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
10.1.6 PI—Programming Interface Register (USB EHCI—D29:F0)
Address Offset: 09h Attribute: RO
Default Value: 20h Size: 8 bits
10.1.7 SCC—Sub Class Code Register (USB EHCI—D29:F0)
Address Offset: 0Ah Attribute: RO
Default Value: 03h Size: 8 bits
12 Received Target Abort (RTA) — R/WC.
0 = No target abort received by EHC on memory access.
1 = This bit is set when EHC, as a master, receives a target abort status on a memory access. This
is treated as a Host Error and halts the DMA engines. This event can optionally generate an
SERR# by setting the SERR# Enable bit (D29:F0:04h, bit 8).
11 Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function responds to a
cycle with a target abort. There is no reason for this to happen, so this bit is hardwired to 0.
10:9 DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion. Read Only
8 Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error detected on USB2.0 read completion packet.
1 = This bit is set by Intel® Xeon® Processor D-1500 Product Family when a data parity error is
detected on a USB 2.0 read completion packet on the internal interface to the EHCI host
controller and bit 6 of the Command register is set to 1.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.
4 Capabilities List (CAP_LIST) — RO. Hardwired to 1 indicating that offset 34h contains a valid
capabilities pointer.
3 Interrupt Status
— RO. This bit reflects the state of this function’s interrupt at the input of the
enable/disable logic.
0 = This bit will be 0 when the interrupt is de-asserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved
Bit Description
Bit Description
7:0 Revision ID — RO. This field indicates the device specific revision identifier.
Bit Description
7:0 Programming Interface — RO. A value of 20h indicates that this USB 2.0 host controller conforms
to the EHCI Specification.
Bit Description
7:0 Sub Class Code (SCC) — RO.
03h = Universal serial bus host controller.