Datasheet

EHCI Controller Registers (D29:F0)
Intel® Xeon® Processor D-1500 Product Family 393
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
10.1.4 PCISTS—PCI Status Register (USB EHCI—D29:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0290h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
8 SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# in the following
cases:
• When it receive a completion status other than “successful” for one of its DMA initiated memory
reads on it’s internal interface.
• When it detects an address or command parity error and the Parity Error Response bit is set.
• When it detects a data parity error (when the data is going into the EHC) and the Parity Error
Response bit is set.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6 Parity Error Response (PER) — R/W.
0 = The EHC is not checking for correct parity (on its internal interface).
1 = The EHC is checking for correct parity (on its internal interface) and halt operation when bad
parity is detected during the data phase.
Note: If the EHC detects bad parity on the address or command phases when the bit is set to 1,
the host controller does not take the cycle. It halts the host controller (if currently not
halted) and sets the Host System Error bit in the USBSTS register. This applies to both
requests and completions from the system interface.
This bit must be set in order for the parity errors to generate SERR#.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to act as a master on the PCI bus for
USB transfers.
1 Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory Space
registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F0:10h) for USB 2.0
should be programmed before this bit is set.
0 I/O Space Enable (IOSE) — RO. Hardwired to 0.
Bit Description
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = This bit is set by Intel® Xeon® Processor D-1500 Product Family when a parity error is seen by
the EHCI controller, regardless of the setting of bit 6 or bit 8 in the Command register or any
other conditions.
14 Signaled System Error (SSE) — R/WC.
0 = No SERR# signaled by Intel® Xeon® Processor D-1500 Product Family .
1 = This bit is set by Intel® Xeon® Processor D-1500 Product Family when it signals SERR#
(internally). The SER_EN bit (bit 8 of the Command Register) must be 1 for this bit to be set.
13 Received Master Abort (RMA) — R/WC.
0 = No master abort received by EHC on a memory access.
1 = This bit is set when EHC, as a master, receives a master abort status on a memory access. This
is treated as a Host Error and halts the DMA engines. This event can optionally generate an
SERR# by setting the SERR# Enable bit
.