Datasheet
EHCI Controller Registers (D29:F0)
392 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: All configuration registers in this section are in the core well and reset by a core well
reset and the D3-to-D0 warm reset, except as noted.
10.1.1 VID—Vendor Identification Register (USB EHCI—D29:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
10.1.2 DID—Device Identification Register (USB EHCI—D29:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
10.1.3 PCICMD—PCI Command Register (USB EHCI—D29:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
64h PDO Port Disable Override Register 0000h R/W, RO
66h RMHDEVR RMH Device Removable Field Register 0000h R/W, RO
68h–6Bh LEG_EXT_CAP USB EHCI Legacy Support Extended
Capability
00000001h R/W, RO
6Ch–6Fh LEG_EXT_CS USB EHCI Legacy Extended Support
Control/Status
00000000h R/W, R/WC,
RO
70h–73h SPECIAL_SMI Intel Specific USB 2.0 SMI 00000000h R/W, R/WC
74h–77h OCMAP Over-Current Mapping C0300C03h R/W
78h–7Dh — Reserved — —
7Eh–7Fh RMHWKCTL RMH Wake Control 0000h R/W, RO
80h ACCESS_CNTL Access Control 00h R/W, RO
84h–87h EHCIIR1 EHCI Initialization Register 1 01h R/W
98h FLR_CID FLR Capability ID 13h RO
99h FLR_NEXT FLR Next Capability Pointer 00h RO
9Ch FLR_CTRL FLR Control 00h R/W, RO
9Dh FLR_STS FLR Status 00h RO
Table 10-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Value Attribute
Bit Description
15:0 Vendor ID — RO. This is a 16-bit value assigned to Intel.
Bit Description
15:0 Device ID — RO. This is a 16-bit value assigned to Intel® Xeon® Processor D-1500 Product Family
USB EHCI controller.
Bit Description
15:11 Reserved Read Only
10 Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
The corresponding Interrupt Status bit (D29:F0:06h, bit 3) is not affected by the interrupt enable.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.