Datasheet

Intel® Xeon® Processor D-1500 Product Family and System Clocks
Intel® Xeon® Processor D-1500 Product Family 39
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2.5.1.2 SSCTRIPARAM_PCHPCIE100—100 MHz Intel® Xeon® Processor D-
1500 Product Family PCIe Clock SSC Triangle Register
Attribute: R/W
Default Value: 12404038h Size: 32-bit
2.5.1.3 SSCCTL_PCHPCIE100—100 MHz Intel® Xeon® Processor D-1500
Product Family PCIe* Clock SSC Control Register
Attribute: R/W
Default Value: 00000000h Size: 32-bit
2.5.1.4 DIV_PCI33—33 MHz Single Ended Clock Divide and Spread Enable
Register
Attribute: R/W
Default Value: 00030203h Size: 32-bit
Bit Description
31:0 100 MHz PCIe Clock SSC Triangle Control — R/W. This register is used for Intel® Xeon®
Processor D-1500 Product Family PCIe clock SSC control. Firmware may program this field with
various values when SSC is enabled.
Bit Description
31:0 100 MHz PCIe Clock SSC Control — R/W. This register is used for Intel® Xeon® Processor D-
1500 Product Family PCIe clock SSC control. Should only use the default value.
Bit Description
31:23 Reserved
22:21 DIV_PCI33 Clock Mux Control 1— R/W. Internal multiplex control for 33.33 MHz clock
direction.
00 = 33.33 MHz SSC (Default)
10 = 33.33 MHz non-SSC
All other values are not supported.
20:17 Reserved
16 DIV_PCI33 Clock Mux Control 2 — R/W. Internal multiplex control for 33.33 MHz clock
direction.
0 = 33.33 MHz SSC (Default)
1 = 33.33 MHz non-SSC
15 DIV_PCI33 Enable/Disable — R/W.
0 = Enables divider for SSC. (Default)
1 = Enables divider with no SSC.
14:13 Reserved
12 DIV_PCI33 Clock Internal Gating Enable — R/W.
0 = 33.33 MHz SSC (Default)
1 = 33.33 MHz non-SSC
11 Reserved
10:8 DIV_PCI33 Divider Selection — R/W.
010 =Divide by 3 from an internal 100 MHz clock source for 33 MHz single ended clocks.
All other values are not supported.
7 Reserved
6:0 DIV_PCI33 Divider Value Counter — R/W. Bit value only valid when use in non-SSC
configurations.
001_1001 = 33.33 MHz frequency
All other values are not supported.