Datasheet
SATA Controller Registers (D31:F5)
388 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.3.2.2 PxSCTL — Serial ATA Control Register (D31:F5)
Address Offset: Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
SDATA when SINDX.RIDX is 01h.
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to the SControl register result in an action being taken by Intel® Xeon® Processor D-
1500 Product Family or the interface. Reads from the register return the last value
written to it.
Bit Description
31:20 Reserved
19:16 Port Multiplier Port (PMP) — RO. This field is not used by AHCI.
15:12 Select Power Management (SPM) — RO. This field is not used by AHCI.
11:8 Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which power states
Intel® Xeon® Processor D-1500 Product Family is allowed to transition to:
All other values reserved
7:4 Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface. This speed is
limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
All other values reserved.
Intel® Xeon® Processor D-1500 Product Family Supports Gen 1 communication rates (1.5 Gb/s),
Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6 Gb/s).
3:0 Device Detection Initialization (DET) — R/W. Controls Intel® Xeon® Processor D-1500 Product
Family ’s device detection and interface initialization.
All other values reserved.
Value Description
0h No interface restrictions
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
Value Description
0h No device detection or initialization action requested
1h Perform interface communication initialization sequence to establish
communication. This is functionally equivalent to a hard reset and results in
the interface being reset and communications re-initialized
4h Disable the Serial ATA interface and put Phy in offline mode