Datasheet
SATA Controller Registers (D31:F5)
386 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h Attribute: R/W
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined Size: 32 bits
9.3 Serial ATA Index/Data Pair Superset Registers
All of these I/O registers are in the core well. They are exposed only when SCC is 01h
(that is, IDE programming interface) and the controller is not in combined mode. These
are Index/Data Pair registers that are used to access the SerialATA superset registers
(SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for these
registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are
reserved for future expansion. Software-write operations to the reserved locations shall
have no effect while software-read operations to the reserved locations shall return 0.
9.3.1 SINDX—SATA Index Register (D31:F5)
Address Offset: SIDPBA + 00h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and
SERR. The I/O space for these registers is allocated through SIDPBA.
9.3.2 SDATA—SATA Index Data Register (D31:F5)
Address Offset: SIDPBA + 04h Attribute: R/W
Default Value: All bits undefined Size: 32 bits
Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and
SERR. The I/O space for these registers is allocated through SIDPBA.
Bit Description
31:2 Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits [31:2] of the
memory location of the Physical Region Descriptor (PRD). The Descriptor Table must be DWord-
aligned. The Descriptor Table must not cross a 64-K boundary in memory.
1:0 Reserved
Bit Description
31:16 Reserved
15:8 Port Index (PIDX)— R/W. This Index field is used to specify the port of the SATA controller at
which the port-specific SSTS, SCTL, and SERR registers are located.
00h = Primary Master (Port 4)
02h = Secondary Master (Port 5)
All other values are Reserved.
7:0 Register Index (RIDX)— R/W. This Index field is used to specify one out of three registers
currently being indexed into.
00h = SSTS
01h = SCTL
02h = SERR
All other values are Reserved.