Datasheet

SATA Controller Registers (D31:F5)
Intel® Xeon® Processor D-1500 Product Family 385
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)
Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO
Secondary: BAR + 0Ah
Default Value: 00h Size: 8 bits
0 Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot be stopped
and then resumed. If this bit is reset while bus master operation is still active (that is, the Bus
Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus Master IDE Status register for that
IDE channel is set) and the drive has not yet finished its data transfer (the Interrupt bit in the
Bus Master IDE Status register for that IDE channel is not set), the bus master command is said
to be aborted and data transferred from the drive may be discarded instead of being written to
system memory.
1 = Enables bus master operation of the controller. Bus master operation does not actually start
unless the Bus Master Enable bit (D31:F5:04h, bit 2) in PCI configuration space is also set. Bus
master operation begins when this bit is detected changing from 0 to 1. The controller will
transfer data between the IDE device and memory only when this bit is set. Master operation
can be halted by writing a 0 to this bit.
Note: This bit is intended to be cleared by software after the data transfer is completed, as
indicated by either the Bus Master IDE Active bit being cleared or the Interrupt bit of the
Bus Master IDE Status register for that IDE channel being set, or both. Hardware does not
clear this bit automatically. If this bit is cleared to 0 prior to the DMA data transfer being
initiated by the drive in a device to memory data transfer, then Intel® Xeon® Processor D-
1500 Product Family will not send DMAT to terminate the data transfer. SW intervention
(such as, sending SRST) is required to reset the interface in this condition.
Bit Description
Bit Description
7 PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set.
6 Reserved
5 Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. Intel® Xeon® Processor D-1500 Product Family does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
4:3 Reserved
2 Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not disabled
interrupts using the IEN bit of the Device Control Register (see chapter 5 of the Serial ATA
Specification, Revision 1.0a).
1 Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
data on PCI.
0 Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by Intel® Xeon® Processor D-1500 Product Family when the last transfer for
a region is performed, where EOT for that region is set in the region descriptor. It is also cleared
by Intel® Xeon® Processor D-1500 Product Family when the Start Bus Master bit
(D31:F5:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read as a 0, all
data transferred from the drive during the previous bus master command is visible in system
memory, unless the bus master command was aborted.
1 = Set by Intel® Xeon® Processor D-1500 Product Family when the Start bit is written to the
Command register.