Datasheet

SATA Controller Registers (D31:F5)
384 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.2 Bus Master IDE I/O Registers (D31:F5)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in D31:F2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
affect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. The description
of the I/O registers is shown in Ta b l e 9- 2 .
9.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5)
Address Offset: Primary: BAR + 00h Attribute: R/W
Secondary: BAR + 08h
Default Value: 00h Size: 8 bits
Table 9-2. Bus Master IDE I/O Register Address Map
BAR+
Offset
Mnemonic Register Default Attribute
00 BMICP Command Register Primary 00h R/W
01 — Reserved — RO
02 BMISP Bus Master IDE Status Register Primary 00h R/W, R/WC,
RO
03 — Reserved — RO
04–07 BMIDP Bus Master IDE Descriptor Table Pointer Primary xxxxxxxxh R/W
08 BMICS Command Register Secondary 00h R/W
09 — Reserved — RO
0Ah BMISS Bus Master IDE Status Register Secondary 00h R/W, R/WC,
RO
0Bh — Reserved — RO
0Ch–0Fh BMIDS Bus Master IDE Descriptor Table Pointer Secondary xxxxxxxxh R/W
Bit Description
7:4 Reserved
3 Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master transfer: This
bit must NOT be changed when the bus master function is active.
0 = Memory reads
1 = Memory writes
2:1 Reserved