Datasheet

SATA Controller Registers (D31:F5)
Intel® Xeon® Processor D-1500 Product Family 383
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.32 FLRCLV—FLR Capability Length and Value Register (SATA–
D31:F5)
Address Offset: B2h–B3h Attribute: RO, R/WO
Default Value: 2006h Size: 16 bits
Function Level Reset:No (Bits 9:8 only)
When FLRCSSEL = 0, this register is RO:
9.1.33 FLRCTRL—FLR Control Register (SATA–D31:F5)
Address Offset: B4h–B5h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
9.1.34 ATC—APM Trapping Control Register (SATA–D31:F5)
Address Offset: C0h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This SATA controller does not support legacy I/O access. Therefore, this register is
reserved. Software shall not change the default values of the register; otherwise, the
result will be undefined.
9.1.35 ATC—APM Trapping Control Register (SATA–D31:F5)
Address Offset: C4h Attribute: R/WC
Default Value: 00h Size: 8 bits
Note: This SATA controller does not support legacy I/O access. Therefore, this register is
reserved. Software shall not change the default values of the register; otherwise the
result will be undefined.
Bit Description
15:10 Reserved
9 FLR Capability — R/WO. This field indicates support for Function Level Reset.
8 TXP Capability — R/WO. This field indicates support for the Transactions Pending (TXP) bit. TXP
must be supported if FLR is supported.
7:0 Capability Length — RO. This field indicates the number of bytes of the Vendor Specific capability
as required by the PCI specification. It has the value of 06h for FLR Capability.
Bit Description
15:9 Reserved
8 Transactions Pending (TXP) — RO.
0 = Completions for all Non-Posted requests have been received by the controller.
1 = Controller has issued Non-Posted request which has not been completed.
7:1 Reserved
0 Initiate FLR — R/W. Used to initiate FLR transition. A write of 1 indicates FLR transition.
Bit Description
7:0 Reserved
Bit Description
7:0 Reserved