Datasheet

SATA Controller Registers (D31:F5)
382 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.29 SATACR0—SATA Capability Register 0 (SATA–D31:F5)
Address Offset: A8h–ABh Attribute: RO, R/WO
Default Value: 0010B012h Size: 32 bits
Function Level Reset: No (Bits 15:8 only)
When SCC is 01h, this register is read-only 0.
9.1.30 SATACR1—SATA Capability Register 1 (SATA–D31:F5)
Address Offset: ACh–AFh Attribute: RO
Default Value: 00000048h Size: 32 bits
When SCC is 01h, this register is read-only 0.
9.1.31 FLRCID—FLR Capability ID Register (SATA–D31:F5)
Address Offset: B0h–B1h Attribute: RO
Default Value: 0009h Size: 16 bits
0 Port 4 Enabled (P4E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
This bit is read-only 0 when MAP.SPD[0]= 1 or is a PCIe Port.
Bits Description
Bit Description
31:24 Reserved
23:20 Major Revision (MAJREV) — RO. Major revision number of the SATA Capability Pointer
implemented.
19:16 Minor Revision (MINREV) — RO. Minor revision number of the SATA Capability Pointer
implemented.
15:8 Next Capability Pointer (NEXT) — R/WO. Points to the next capability structure.
7:0 Capability ID (CAP) — RO. The value of 12h has been assigned by the PCI SIG to designate the
SATA capability pointer.
Bit Description
31:16 Reserved
15:4 BAR Offset (BAROFST) — RO. Indicates the offset into the BAR where the index/Data pair are
located (in DWord granularity). The index and Data I/O registers are located at offset 10h within the
I/O space defined by LBAR (BAR4). A value of 004h indicates offset 10h.
3:0 BAR Location (BARLOC) — RO. Indicates the absolute PCI Configuration Register address of the
BAR containing the Index/Data pair (in DWord granularity). The Index and Data I/O registers reside
within the space defined by LBAR (BAR4) in the SATA controller. a value of 8h indicates and offset of
20h, which is LBAR (BAR4).
Bit Description
15:8 Next Capability Pointer — RO. A value of 00h indicates the final item in the Capability List.
7:0 Capability ID — RO. The value of this field depends on the FLRCSSECL bit.
If FLRCSSEL = 0, this field is 13h
If FLRCSSEL = 1, this field is 00h.