Datasheet

SATA Controller Registers (D31:F5)
Intel® Xeon® Processor D-1500 Product Family 381
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.27 MAP—Address Map Register (SATA–D31:F5)
Address Offset: 90h–91h Attribute: R/W, R/WO, RO
Default Value: 0000h Size: bits
Function Level Reset: No (Bits 9:8 only)
9.1.28 PCS—Port Control and Status Register (SATA–D31:F5)
Address Offset: 92h–93h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Function Level Reset: No
By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled
by software, the ports can transition between the on, partial, and slumber states and
can detect devices. When disabled, the port is in the “off” state and cannot detect any
devices.
If an AHCI-aware or RAID enabled operating system is being booted, then system BIOS
shall insure that all supported SATA ports are enabled prior to passing control to the
OS. Once the AHCI aware OS is booted, it becomes the enabling/disabling policy owner
for the individual SATA ports. This is accomplished by manipulating a port PxSCTL and
PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of
the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-
boot software must insure that these bits are set to 1 prior to booting the OS,
regardless as to whether or not a device is currently on the port.
Bits Description
15:8 Reserved
7:6 SATA Mode Select (SMS) — R/W. Software programs these bits to control the mode in which the
SATA Controller should operate.
00b = IDE Mode
All other combinations are reserved.
5:2 Reserved
1:0 Map Value (MV)— Reserved.
Bits Description
15:10 Reserved
9 Port 5 Present (P5P) — RO. The status of this bit may change at any time. This bit is cleared
when the port is disabled using P1E. This bit is not cleared upon surprise removal of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
8 Port 4 Present (P4P) — RO. The status of this bit may change at any time. This bit is cleared
when the port is disabled using P0E. This bit is not cleared upon surprise removal of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
7:2 Reserved
1 Port 5 Enabled (P5E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
This bit is read-only 0 when MAP.SPD[1]= 1 pr is a PCIe Port.