Datasheet

Intel® Xeon® Processor D-1500 Product Family and System Clocks
38 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2.5 Integrated Clock Controller (ICC) Registers
This section describes all registers and base functionality that is related to the
Integrated Clock Controller. The ICC registers are not visible using PCI Configuration
access and it is not mapped to I/O memory as other devices within Intel® Xeon®
Processor D-1500 Product Family. The control settings for the ICC clock structure is
located in registers directly under the control of the Intel Management Engine
(Intel ME).
ICC register access is only accessible using Intel ME FW and must be programmed
using available FW access tools. The ICC registers disclosed in this chapter cover user
adjustable features within the ICC subsystem programmable through available FW
access tools.
2.5.1 ICC Registers under Intel
®
Management Engine (Intel
®
ME) Control
2.5.1.1 SSCDIVINTPHASE_PCHPCIE100—100 MHz Intel® Xeon® Processor D-
1500 Product Family PCIe Clock SSC Divider Integer Phase Register
Attribute: R/W
Default Value: 00000032h Size: 32-bit
Table 2-5. ICC Registers under Intel
®
Management Engine (Intel
®
ME) Control
Mnemonic Register Name Default
SSCDIVINPHASE_PCHPCIE100 100 MHz SSC Divider Integer Phase Control for
Intel® Xeon® Processor D-1500 Product Family
PCIe Clocks
0000_0032h
SSCTRIPARAM_PCHPCIE100 100 MHz SSC Triangle Parameter for Intel® Xeon®
Processor D-1500 Product Family PCIe Clocks
1240_4038h
SSCCTL_PCHPCIE100 100 MHz SSC Control for Intel® Xeon® Processor
D-1500 Product Family PCIe Clocks
0000_0000h
DIV_PCI33 33 MHz Single Ended Clock Divide and
Spread Enable
0003_0203h
DIV_FLEX4824 48/24 MHz Single Ended Flex Clock Divide Enable 0003_0103h
OCKEN Output Clock Enables 7DFF_0F8Fh
SEFLXBP Single Ended Flex Buffer Parameters 0000_9999h
SEPCICLKBP Single Ended 33 MHz Clock Buffer Parameters 0009_9999h
DCOSS Differential Clock Out Source Select 0000_0400h
SECOSS Single Ended Clock Out Source Select 0000_2516h
MCSS Miscellaneous Clock Source Select 0000_0001h
PLLRCS PLL Reference Clock Select 0001_1114h
ICCCTL ICC Control 0000_0008h
PMPCI Power Management 33 MHz Clock 0000_0000h
PM1PCIECLK Power Management 1 PCIe Clock 7654_3210h
PM2PCIECLK Power Management 2 PCIe Clock 0000_0098h
Bit Description
31:0 100 MHz PCIe* Clock SSC Phase Control — R/W. This register is used for tuning PCIe Adaptive
Clocking frequency. Firmware may program this field with various values when adjusting PCIe
adaptive clocking values.