Datasheet

SATA Controller Registers (D31:F5)
378 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These
bits have no effect on hardware.
9.1.21 SDMA_CNT—Synchronous DMA Control Register (SATA–
D31:F5)
Address Offset: 48h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
9.1.22 SDMA_TIM—Synchronous DMA Timing Register (SATA–
D31:F5)
Address Offset: 4Ah–4Bh Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
15 IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
0 = Disable.
1 = Enables Intel® Xeon® Processor D-1500 Product Family to decode the associated Command
Block and Control Block.
14:12 IDE_TIM Field 2 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
11:10 Reserved
9:0 IDE_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no effect
on hardware.
Bit Description
7:3 Reserved
2 Secondary Master ATAxx Enable (SDAE0) — R/W.
0 = Disable (default)
1 = Enable DMA timing modes for the secondary master device.
1 Reserved
0 Primary Master ATAxx Enable (PDAE0) — R/W.
0 = Disable (default)
1 = Enable DMA timing modes for the primary master device
Bit Description
15:10 Reserved
9:8 SDMA_TIM Field 2— R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.
7:2 Reserved
1:0 SDMA_TIM Field 1 — R/W. This field is R/W to maintain software compatibility. This field has no
effect on hardware.