Datasheet

SATA Controller Registers (D31:F5)
Intel® Xeon® Processor D-1500 Product Family 377
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.15 SVID—Subsystem Vendor Identification Register (SATA–
D31:F5)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset:No
9.1.16 SID—Subsystem Identification Register (SATA–D31:F5)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
9.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5)
Address Offset: 34h Attribute: RO
Default Value: 70h Size: 8 bits
9.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
9.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5)
Address Offset: 3Dh Attribute: RO
Default Value: See Register Description Size: 8 bits
Bit Description
15:0 Subsystem Vendor ID (SVID) — R/WO. Value is written by BIOS. No hardware action taken on
this value.
Bit Description
15:0 Subsystem ID (SID) — R/WO. Value is written by BIOS. No hardware action taken on this value.
Bit Description
7:0 Capabilities Pointer (CAP_PTR) — RO. Indicates that the first capability pointer offset is 70h if
the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of 01).
Bit Description
7:0 Interrupt Line — R/W. This field is used to communicate to software the interrupt line that the
interrupt pin is connected to. These bits are not reset by FLR.
Bit Description
7:0 Interrupt Pin — RO. This reflects the value of D31IP.SIP1 (Chipset Config Registers:Offset
3100h:bits 11:8).