Datasheet

SATA Controller Registers (D31:F5)

376 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

Note: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command Block.

9.1.13 BAR — Legacy Bus Master Base Address Register (SATA–

D31:F5)

Address Offset: 20h–23h Attribute: R/W, RO

Default Value: 00000001h Size: 32 bits

The Bus Master IDE interface function uses Base Address register 5 to request a 16-

byte I/O space to provide a software interface to the Bus Master functions. Only

12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits

[15:4] are used to decode the address.

9.1.14 SIDPBA — SATA Index/Data Pair Base Address Register

(SATA–D31:F5)

Address Offset: 24h–27h Attribute: R/W, RO

Default Value: 00000000h Size: 32 bits

When SCC is 01h

When the programming interface is IDE, the register represents an I/O BAR allocating

16B of I/O space for the I/O mapped registers defined in Section 9.3. While 16B of

locations are allocated, some maybe reserved.

1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.

Bit Description

31:16 Reserved

15:5 Base Address — R/W. This field provides the base address of the I/O space (16 consecutive I/O

locations).

4 Base Address 4 (BA4)— R/W.

When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space.

3:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.

Bit Description

31:16 Reserved

15:4 Base Address (BA) — R/W. Base address of register I/O space

3:1 Reserved

0 Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.