Datasheet

SATA Controller Registers (D31:F5)
Intel® Xeon® Processor D-1500 Product Family 373
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
9.1.4 PCISTS — PCI Status Register (SATA–D31:F5)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 02B0h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — R/W. This bit controls Intel® Xeon® Processor D-1500 Product
Family ability to act as a PCI master for IDE Bus Master transfers. This bit does not impact the
generation of completions for split transaction commands.
1 Memory Space Enable (MSE) — RO. This controller does not support AHCI; therefore, no memory
space is required.
0 I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
Bus Master I/O registers.
1 = Enable. The Base Address register for the Bus Master registers should be programmed before
this bit is set.
Bit Description
Bit Description
15 Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
14 Signaled System Error (SSE) — RO. Hardwired to 0.
13 Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
12 Reserved
11 Signaled Target Abort (STA) — RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
8 Data Parity Error Detected (DPED) — R/WC. For Intel® Xeon® Processor D-1500 Product Family
, this bit can only be set on read completions received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted,
and the parity error response bit (bit 6 of the command register) is set.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66MHz Capable (66MHZ_CAP) — RO. Hardwired to 1.
4 Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The
minimum requirement for the capabilities list must be PCI power management for the SATA
controller.
3 Interrupt Status (INTS) — RO. Reflects the state of INTx# messages, IRQ14 or IRQ15.
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the command register
[offset 04h]).
1 = Interrupt is to be asserted
2:0 Reserved